1. Technical Field
The present invention relates generally to data processing systems and in particular to methods for issuing load-dependent instructions within data processing systems.
2. Description of the Related Art
Early microprocessors executed only one instruction at a time and executed instructions in an order determined by the compiled machine-language program running on the microprocessor. Such microprocessors are known as “sequential” microprocessors. Various techniques, such as pipelining, superscaling, and speculative instruction execution, are utilized to improve the performance of sequential microprocessors. Pipelining breaks the execution of instructions into multiple stages, in which each stage corresponds to a particular execution step. Pipelined designs enable new instructions to begin executing before previous instructions are finished, thereby increasing the rate at which instructions can be executed.
“Superscalar” microprocessors typically include multiple pipelines and can process instructions in parallel using two or more instruction execution pipelines in order to execute multiple instructions per microprocessor clock cycle. Parallel processing requires that instructions can be dispatched for execution at a sufficient rate. However, the execution rate of microprocessors has typically outpaced the ability of memory devices and data buses to supply instructions to the microprocessors. Therefore, conventional microprocessors utilize one or more levels of on-chip cache memory to increase memory access rates.
Conventional microprocessors utilize speculative instruction execution to address pipeline stalls by enabling a second instruction that is data dependent on a first instruction to enter an execution pipeline before the first instruction has passed completely through the execution pipeline. Thus, in speculative instruction microprocessors, the data dependent second instruction, which is often referred to as a “consumer” instruction, depends on the first instruction, which is referred to as a “producer” instruction.
In microprocessors that utilize speculative instruction execution, there is a delay between the decision to issue an instruction and the actual execution of the instruction. For example, in the case of load instructions, there may be a significant delay between the issue of a load instruction and the corresponding data fetch from cache memory. A consumer instruction, dependent on a delayed load producer instruction, may be issued before confirmation by the cache system that the load data required is available in the cache. When the required data is not found in the cache, dependent consumer instructions can execute and access incorrect data.